Capacitor-less LDO Design Techniques for Portable Applications in Nanometer CMOS

Abstract

In the realm of modern electronics, effective power management is crucial, especially with the prevalence of System-on-Chip (SoC) technologies. Traditional Low-Dropout Voltage Regulators (LDOs) often rely on output capacitors, which can incur additional costs, increase board sizes, and expand pin counts. This study focuses on the development of two external capacitor-less Low-Dropout Voltage Regulator (LDO) designs in 55nm CMOS technology for portable applications. The first LDO design spans a voltage range of 1to4V,maintainingastable1.2 Voutputacrossloadsfrom0.2to 50 mA,withapowerconsumptionof1mWonly. UsingaTransient EnhancementCircuit, It exhibits minimal voltage spikes (below 150 mV), a 0.1 us settling time, and a quiescent current of 59 µA under maximum load. The second LDO design integrates a slew rate en hancement circuit for improved transient responses. It remains sta ble throughout a0–50mAfullloadrangewithoutanoutputcapaci tor. The LDO’s output voltage recovers within 0.4 µs with a voltage spike of less than 40 mV, demonstrating enhanced DC load control (0.031 mV/mA)consuming71µW.Itoperateswithaquiescentcur rent of 22 µA and a 200 mV dropout voltage at 1V supply Voltage andregulate the circuit output Voltage at 0.8V. Both LDOs offer effi cient load and line transient responses, reduced settling times, and resilience to process, voltage, and temperature variations, ensuring consistent and reliable performance