LDO DESIGN FOR WEARABLE SYSTEMS IN NANOMETER CMOS TECHNOLOGY

Abstract

In modern electronics, two key priorities stand out: maximizing battery life and optimizing chip space utilization. Low dropout regulators (LDOs) play a crucial role in enhancing the performance of wearable devices by extending battery longevity. The conventional LDO design typically requires large ex ternal capacitors, it consumes considerable die area. To reduce the area, an innovative capacitor-less LDO is used. This thesis study two capacitor-less LDOdesign as the transistor level simulation in SMIC 55nm CMOS Technol ogy. The first ldo design integrates a comparator circuit, to improve transient response. It has a input voltage range of 0.8-V to 2.4-V and maintains output almost 0.8-V over load from 0 to 50-mA with power consumption of 90µW. The circuit output ripple is below 40-mV. The settling time of 0.2µs and a quiescent current of 26µA at maximum load. The second capacitor-less LDO circuit utilizes a folded cascode amplifier, it can achieve settling time reduc tion twice of the first design. It remains stable without an output capacitor throughout a complete load range of 0.1-mA to 50-mA. The output voltage recovers within 0.1µs with a voltage ripple of less than 100-mV with power consumption of 62µW. The circuit has a quiescent current of 22µA, and a 200mV dropout voltage at 0.8 to 2V. It regulates the circuit output voltage to 0.6-V. Both LDOs offer efficient load and line transient responses, reduced settling times, and resilience to process, voltage, and temperature variations, ensuring consistent and reliable performance