Design and Development of Serial RISC-V Soft Microprocessor Core

Abstract

It 's a fact! That in modern microprocessor designs, energy efficiency and performance are two critical factors that drive research and innovation. As traditional approach to design the microprocessor has employed parallel processing techniques to enhance performance, but such approach often come with high power and area consumption. In recent few decades, we wit nessed the remarkable advancement in microprocessor deign leading to increased computational power and energy efficiency in modern computing system. Therefore, the investigation of ilmo vative architectures that utilize bit-serial processing approach is an important field of research in processor design. This thesis work presents the design, implementation, and performance eval uation of a bit-serial approach to design a 32-bit RISC-V microprocessor. Aiming to leverage the benefits of bit-serial processing. The proposed microprocessor deign execute t he RISC-V instructions using bit-serial execution (one-bit per clock edge). This technique substantially reduce hardware complexity, increased energy efficiency and achieve higher clock frequency. The proposed microprocessor is pipelined and covered almost all the data, control and struc tural hazards. This design is made by using Hardware descriptive language name Verilog. And duly verified using Coogle Design Verification Environment. And its performance evaluation is conducted. Through a comprehensive set of benchmarks to compare the bit-serial RISC-V microprocessor against with the conventional RISCV microprocessor and state of the art mi croarchitectures. The benchmarks encompass diverse work loads, including integer arithmetic, memory access, and control intensive t asks. Matrices such as power consumption, throughput, energy effi ciency and area efficiency are considered to assess the effectiveness of the proposed archi teet ure.